The present disclosure relates to a semiconductor memory device, and more particularly, to a precharge voltage supply circuit, which is capable of reducing the amount of leakage current leaked through a bridge formed between a bit line and a word line in a power down mode and rapidly recovering a bit line precharge voltage level when exiting the power down mode.
As semiconductor devices are being highly integrated in recent years, an occupation area of each component in semiconductor devices is gradually decreasing. Particularly, in the case of dynamic random access memories (DRAMs), the likelihood that a bridge phenomenon may occur between a word line and a bit line is increasing due to a reduction in a gate pitch. The bridge phenomenon between the word line and the bit line is mainly attributed to a gate residue that remains between the word line and the bit line, i.e., a polysilicon layer is not completely etched away during an etch process to form a gate, or attributed to a portion of a nitride layer disposed over the gate that is undesirably removed during a chemical mechanical polishing (CMP) process and thus that portion has a weakness.
FIG. 1 illustrates a word line and a bit line in a semiconductor memory device. If the bridge is formed between the word line and the bit line illustrated in FIG. 1, the bridge serves as a current path therebetween. Accordingly, charges accumulated in the bit line flow through the current path in a standby mode of the semiconductor memory device, thus generating undesirable leakage current between the word line and the bit line in the standby mode. Of course, it may be possible to prevent erroneous operations caused by formation of a bridge by substituting the failed cell, in which the bridge is formed, with a redundant cell. In this case, however, the failed cell still remains in the semiconductor device. This makes the leakage current keep on flowing into the failed cells.
In real products, for example, 32M pseudo static RAMs (SRAMs), a leakage current flows through a bridge with the magnitude of approximately 9 μA per one “R+C”. If, however, the magnitude of leakage current becomes great like above, product yield may be reduced by about 40%.
Therefore, there is a limitation in reducing the leakage current flowing through the bridge using a voltage drop transistor and a bleeder resistor because the bridge formed between the word line and the bit line may have a resistance varied with a failure type of a gate pattern.